Conventional semiconductor devices generally include a semiconductor substrate, such as a silicon substrate, and a plurality of sequentially formed dielectric interlayers such as silicon dioxide and conductive paths or interconnects made of conductive materials. Copper and copper-alloys have recently received considerable attention as interconnect materials because of their superior electro-migration and low resistivity characteristics. The interconnects are usually formed by filling copper in features or cavities etched into the dielectric layers by a metallization process. The preferred method of copper metallization is electroplating. In an integrated circuit, multiple levels of interconnect networks laterally extend with respect to the substrate surface. Interconnects formed in sequential layers can be electrically connected using vias or contacts.
In a typical process, first an insulating layer is formed on the semiconductor substrate. Patterning and etching processes are performed to form features or cavities such as trenches and vias in the insulating layer. Then, a barrier/glue layer and a seed layer are deposited over the patterned surface and a conductor such as copper is electroplated to fill all the features. However, the plating process, in addition to filling the features with copper, also deposits excess copper over the top surface of the substrate. This excess copper is called an “overburden” and needs to be removed during a subsequent process step. In standard plating processes this overburden copper has a large topography since the Electrochemical Deposition (ECD) process coats large features on the wafer in a conformal manner. For example, a wafer with 0.5 micron deep features may be coated with 0.8 micron thick copper by the standard ECD process, to assure complete, defect-free filling of all the features, including those that are wider than about 5 microns. The resulting copper surface then may have a topography that has a step of about 0.5 microns over the large features. Conventionally, after the copper plating, CMP process is employed to first globally planarize this topographic surface and then to reduce the thickness of the overburden copper layer down to the level of the surface of the barrier layer, which is also later removed leaving conductors only in the cavities. CMP is a costly and time consuming process. High pressures used in the CMP processes also damage low-k dielectrics, which are mechanically weaker than the silicon oxide. Therefore, minimizing CMP step in an integration process is a goal for all IC manufacturers. The topography on the wafers also causes problems for the CMP process. Specifically, the large steps such as the 0.5 micron step of the above example over the large features such as 100 micron wide trenches or bond-pads, cause dishing defects after CMP. Therefore, both in terms of cost and enabling features, it is very attractive to have processes that have the ability to yield thinner copper deposits with reduced surface topography on wafers.
During the copper electrodeposition process, specially formulated plating solutions or electrolytes are used. These electrolytes typically contain water, acid (such as sulfuric acid), ionic species of copper, chloride ions and certain additives which affect the properties and the plating behavior of the deposited material. Typical electroplating baths contain at least two of the three types of commercially available additives such as accelerators, suppressors and levelers. It should be noted that these additives are sometimes called different names. For example, the accelerator may be referred to as a brightener and the suppressor as a carrier in the literature. Functions of these additives in the electrolyte and the role of the chloride ion are widely known in the field (see for example, Z. W. Sun and G. Dixit, “Optimized bath control for void-free copper deposition”, Solid State Technology, November 2001, page. 97), although the details of the mechanisms involved may not be fully understood or agreed upon.
Electrodeposition process needs to fill all the features, small and large, on the substrate. FIG. 1A schematically shows the cross sectional view of an exemplary wafer surface with high-aspect ratio vias 10, a medium aspect-ratio trench 11, and a small aspect-ratio pad 12, coated with a barrier/seed layer 13, which is shown as one layer to simplify the drawing. Vias, trenches, and pads are often known as cavities. As is well known in the field, aspect ratio is the ratio of the depth, d, of the features to their smaller lateral dimension or width, w. In our example the depth, d may range from 0.1 microns to 2.0 microns, although deeper features may also be used for certain applications such as packaging applications. The width of the vias 10 may be sub-micron in size and their aspect ratio (d/w) may be in the range of 1-10. The trench 11 may have an aspect ratio of 0.1-1 and the pad 12 may have an aspect ratio of less than 0.1. For a feature depth of for example 0.5 microns, the vias may be 0.1 micron wide, the trench 11 may be 2 micron wide and the pad may be 20 microns wide.
FIG. 1B shows the substrate of FIG. 1A after copper deposition carried out by prior art methods. The solid line 15 indicates the typical topography of the copper film resulting from a typical ECD process employing an additive package containing two additives, accelerator and suppressor species. It is well known that these additives help bottom-up filling of the high aspect-ratio vias 10 with copper. The mechanism of bottom-up fill, however, becomes less and less effective as the aspect ratio of the features become smaller and smaller, and the deposition becomes more and more conformal. The result is shown in FIG. 1B as a small step D1 over the medium size feature or trench 11 and a large step D2 over the large feature or pad 12. It should be noted that magnitude of these steps over the various size features is at most as large as the feature depth, d. The overfill, O, shown over the dense array of vias 10 is typically observed in copper films deposited by the electrolytes containing two-component additive package of this example. As can be seen in FIG. 1B, the surface topography of the copper film is large and this presents challenges in the CMP step as described earlier.
Several developments have been provided by prior art methods to improve the copper topography depicted by the solid line 15 in FIG. 1B. To reduce or eliminate the overfill O, a third additive, leveler, is added into the electrolyte formulation. By controlling the concentration of the additive carefully, the profile of copper over the dense array of vias 10 could be made flat, which is shown as the dotted line 16 in FIG. 1B. U.S. Pat. No. 6,346,479 B1 describes a method where copper is deposited in a non-conformal electroplating process to fill a portion of the features. A second electroplating process is then performed to conformally deposit copper in the remaining unfilled portion of the openings or features. Such an approach may yield a flat profile over dense array of small features such as vias 10 of our example, as well as possibly over the medium size features such as trench 11 of our example as depicted by dotted lines 16 and 17, respectively. However, as disclosed in U.S. Pat. No. 6,346,479 B1 the second electroplating process conformally deposits copper over the substrate, and therefore can not eliminate the large step D2 over the large features such as the pad 12 shown in our example of FIG. 1B. U.S. Pat. No. 6,350,364 B1 describes a method of electroplating copper in trenches where a first copper deposition step has a first ratio of brightener-to-leveler concentration and a second copper deposition step has a second ratio of brightener-to-leveler concentration that is less than the first ratio of brightener-to-leveler concentration. This way it is reported that the step D1 of FIG. 1B can be reduced. As is well known in the field copper electroplating additives are not operative in the very large features with very small aspect-ratios such as the pad 12 of FIG. 1B. Therefore, the step D2 is not expected to be much reduced or eliminated by such approaches. D2 only gets reduced and eliminated if a very thick copper layer with thickness value close to half the width of the largest feature on the wafer is plated (see e.g. U.S. Pat. No. 5,256,565, Oct. 26, 1993). However, this is not practical considering the fact that many interconnect designs involve feature sizes well above 10 microns.
As the above review demonstrates, some of the prior art techniques aiming to obtain relatively flat copper topography on patterned wafer surfaces may be applicable for the class of wafers with large or medium aspect-ratio features. However, many IC interconnect designs contain features with a wide variety of aspect ratios on a given wafer surface. Especially in multi-level interconnect structures the width of the high-current-carrying lines increase while their aspect-ratios decrease at the higher wiring levels. Therefore, an approach that has the capability of reducing or eliminating surface topography of copper over features with a large range of aspect ratios is needed.
A technique that can reduce or totally eliminate copper surface topography for all feature sizes is the Electrochemical Mechanical Processing (ECMPR). This technique has the ability to eliminate steps D1, D2 and overfill O shown in the example of FIG. 1B, and provide thin layers of planar conductive material on the workpiece surface, or even provide a workpiece surface with no or little excess conductive material. This way, CMP process can be minimized or even eliminated. The term “Electrochemical Mechanical Processing (ECMPR)” is used to include both Electrochemical Mechanical Deposition (ECMD) processes as well as Electrochemical Mechanical Etching (ECME), which is also called Electrochemical Mechanical Polishing (ECMP). It should be noted that in general both ECMD and ECME processes are referred to as electrochemical mechanical processing (ECMPR) since both involve electrochemical processes and mechanical action on the workpiece surface. An exemplary flat copper surface profile resulting from an ECMPR is shown as the flat dotted line, 18, in FIG. 1B.
Descriptions of various ECMPR approaches and apparatus, can be found in the following patents, published applications and pending applications, all commonly owned by the assignee of the present invention: U.S. Pat. No. 6,126,992 entitled “Method and Apparatus for Electrochemical Mechanical Deposition,” U.S. application Ser. No. 09/740,701 entitled “Plating Method and Apparatus that Creates a Differential Between Additive Disposed on a Top Surface and a Cavity Surface of a Workpiece Using an External Influence,” filed on Dec. 18, 2001 and published as U.S. patent application on Feb. 21, 2002 with patent application No. 20020020628, U.S. application filed on Sep. 20, 2001 with Ser. No. 09/961,193 entitled “Plating Method and Apparatus for Controlling Deposition on Predetermined Portions of a Workpiece”, U.S. Application with Ser. No. 09/960,236 filed on Sep. 20, 2001, entitled “Mask Plate Design”, and U.S. application Ser. No. 10/155,828 filed on May 23, 2002 entitled “Low Force Electrochemical Mechanical Processing Method and Apparatus.” These methods can deposit metals in and over cavity sections on a workpiece in a planar manner.